The invention is directed to a semiconductor component with
a) an insulating housing, PA1 b) a metallic, lower mounting plate arranged in the housing, PA1 c) a semiconductor body with at least one logic part and at least one power part with vertical MOS transistors, whereby PA1 d) the semiconductor body has its underside electrically conductively secured on the mounting plate, PA1 e) metallic, lower leads that are electrically connected to the semiconductor body and whereof at least one is electrically connected to the mounting plate.
Semiconductor components with such housings are known. Such housing forms are, for example, the DIL housing (Dual-In-Line) or P-DSO housing (Plastic-Dual-Small-Outline). The former housings are provided for normal mounting and the latter housings are provided for what is referred to as surface mounting (SMD) on printed circuit boards. These housings contain a metallic mounting plate as well as metallic leads that are electrically connected to the mounting plate or, respectively, the components secured on the mounting plate. The mounting plate and the leads are cut from a leadframe.
The semiconductor bodies are then connected to the leads via what is referred to as the bond wire technique.
It has turned out given semiconductor bodies that are composed of a logic part and of a power part with vertical MOS transistors that limits are placed on the realization of extremely low-impedance power switches due to the notoriously known bond wire technique. Given the employment, for example, of eight bond wires connected parallel having 50 .mu.m diameters, an additive on-state dc resistance of approximately 5 m.OMEGA. derives. Given a power switch with, for example, 25 m.OMEGA. overall on-state dc resistance, an added outlay of approximately 4 qmm silicon is caused in the semiconductor body for the compensation of the impedance caused by the parallel bond wires.
Moreover, multiple bondings are generally undesirable and represent a quality problem.